1. Field of the Invention
The present invention generally relates to an interrupt controller for a processor, and more particularly, to an interrupt controller for supporting devices and software configured for a specific interrupt architecture on a processor which is not designed for the specific interrupt architecture.
2. Description of the Related Art
Generally, an interrupt is a signal from a device or a program that causes a processor to stop and determine the next operation to be performed. A processor is typically configured to handle hardware interrupts as well as software interrupts. A hardware interrupt occurs when a hardware device requires a processor to perform a particular operation, for example, when an input/output (I/O) operation is completed, such as reading data from a hard drive. A software interrupt occurs when an application program terminates or requests certain services from the processor.
Several methods are currently being used to pass interrupts (or exceptions) from a given source to a processor or multi-processor bus structure. One typical system used in both personal computing as well as multiprocessor server applications is described by the Advanced Programmable Interrupt Controller (APIC) architecture. In many typical multi-processor computer systems, the APIC interrupt delivery system is used to detect interrupt requests from attached peripheral devices and advise one or more processors to perform the requested services.
FIG. 1 is a block diagram illustrating a multi-processor environment 100 incorporating a conventional APIC architecture. Generally, the multi-processor environment 100 includes a plurality of processors 1101 to 110n having local APICs 1201 to 120n, respectively, an APIC bus 130 and an Input/Output Advanced Programmable Interrupt Controller (IOAPIC) 140. The local APICs 1201 to 120n on the processors 1101 to 110n are coupled to the IOAPIC 140 through the APIC bus 130. The IOAPIC 140 includes a set of interrupt signal inputs 150, an interrupt redirection table, programmable registers, and a messaging unit for sending and receiving APIC messages over the APIC bus 130. The IOAPIC 140 may be situated in an input/output subsystem and configured to receive interrupt requests 160 from peripheral devices. Upon detecting an interrupt request, the IOAPIC 140 transmits an APIC interrupt message which includes an interrupt vector providing information about the interrupt through the APIC bus 130 to the local APICs 1201 to 120n. Each of the local APICs 1201 to 120n is configured to determine whether an interrupt broadcast on the APIC bus 130 should be accepted. The local APICs 1201 to 120n handle all interactions between the respective processors 1101 to 110n and the IOAPIC 140.
Because of the popularity of the APIC architecture, various operating system kernel routines, hardware device drivers, and other hardware and software support are readily available utilizing this interrupt scheme. However, the APIC architecture is only compatible with particular processor platforms, such as the Intel® Architecture IA-32 processors, and is not readily reusable in other platforms, such as a PowerPC® processor platform. Thus, various operating system kernel routines, hardware device drivers and other hardware and software support that are based on the APIC architecture are not compatible with systems based on PowerPC platforms.
Therefore, there exists a need for an apparatus and method for supporting APIC-based software and hardware on a PowerPC platform. Particularly, there is a need for an interface system which can communicate interrupts of APIC-based hardware and software to PowerPC processor cores and return, after processing the interrupts, APIC-based information to the APIC-based hardware and software.